1. Field of the Invention
The present invention relates to test pattern generation and detection. More particularly, the present invention relates to a method and apparatus for generating a test pattern for testing a sequence detection state machine or other circuitry in an electronic device.
2. Background of the Invention
Many electronic devices (e.g. integrated circuits, systems, etc.) have a circuit that receives a serial input stream of data and performs an action in response to the serial input stream.
An electronic device may include a sequence detecting state machine that constantly monitors and evaluates the serial input stream. When a particular pattern is detected in the serial input stream, the sequence detecting state machine causes the electronic device to perform an action. For example, the electronic device may latch data provided on an input bus when the sequence detecting state machine determines that the serial input stream includes a bit pattern that instructs the electronic device to load input data.
When the sequence detecting state machine does not recognize a pattern in the serial input stream, the sequence detecting state machine does not instruct the electronic device to perform an action.
Typically, the serial input stream of data is stored in a register that can then be read by the sequence detecting state machine or by another circuit within the electronic device. Without the use of a sequence detecting state machine, the other circuit may perform an action in response to the serial input stream. For example, the other circuit may comprise an addressable memory circuit and the register may comprise an address register. The address register may be serially loaded with address information of an addressable memory location in the memory circuit. If the address register comprises n bits, there are 2.sup.n possible n-bit address locations that can be loaded into the address register. The serial input stream may comprise all 2.sup.n possible n-bit addresses to test that each address may be properly selected.
If the sequence detecting state machine or other circuit responds to or evaluates an n-bit pattern in the serial stream of data, then in order to completely test whether the sequence detecting state machine or other circuit is functioning properly, 2.sup.n unique patterns must be supplied to the electronic device. The response of the sequence detecting state machine, other circuitry, and the electronic device must be monitored for each of the 2.sup.n unique patterns.
Each unique n-bit pattern may be separately provided to the electronic device. This technique, however, would require a minimum of n.times.2.sup.n cycles to load all n-bit patterns into the electronic device. For example, if n equals three, then it would be possible in 24 cycles (3.times.2.sup.3) to provide to the electronic device the patterns of 000, 001, 010, . . . , 111.
A serial pattern for supplying the 64 combinations of a six-bit pattern has been used to test a sequence detecting state machine which monitors six-bit patterns. The serial pattern comprises: EQU 000000111111010101100110111011010010011100010111100101000110000100000.
However, a method of generating this serial pattern has not been known by others.
It is desirable to generate a serial input stream including all possible n-bit patterns and requiring less than n.times.2.sup.n cycles to serially load into an electronic device. It is also desirable to have the serial input stream be as short as possible to save time in loading the serial input stream into an electronic device under test. Additionally, it is desirable to have a short serial input stream to save time in testing a sequence detecting state machine or other circuitry in an electronic device.
Reducing the time for testing the electronic device saves the device manufacturer and end-user both time and money.